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| Datasheet File OCR Text: |
| geometry process details principal device types mpsh10 mpsh11 cmpth10 cmpth11 gross die per 4 inch wafer 53,730 process CP302 small signal transistor npn - silicon rf transistor chip process epitaxial planar die size 14.5 x 14.5 mils die thickness 9.0 mils base bonding pad area 2.3 x 2.3 mils emitter bonding pad area 2.5 x 2.3 mils top side metalization al - 30,000? back side metalization au - 18,000? www.centralsemi.com r3 (22-march 2010)
process CP302 typical electrical characteristics www.centralsemi.com r3 (22-march 2010) |
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